The RxLOS signal is an output of the analog signal detection circuit of a typical SerDes (serializer/deserializer) core and indicates a loss of signal at the receiver of SerDes. The RxLOS signal can switch between logic 0 and logic 1 in a short period of time and may experience active high or active low glitches for a short period of time. These RxLOS signal glitches can erroneously trigger a set of events in the logic that the SerDes interfaces with. An active high glitch may erroneously indicate a loss of signal at the receiver and may cause the synchronization state machines in the interface logic to be reset. Similarly, an active low glitch may erroneously indicate a recovery of the lost signal at the receiver and may cause the synchronization of the state machines to go out of the reset state.
Glitches must be filtered before the RxLOS signal is used in the logic interfacing of the SerDes core. The size of the glitches that need to be filtered varies with the specific application of the SerDes core and with the protocol. Protocols that implement Out of Band (OOB) signaling like Serial-ATA (SATA) and Serial Attached SCSI (SAS) require that the glitches less than 106 ns wide be filtered while in protocols like FC (Fibre Channel) and Ethernet, glitches larger than 106 ns may need to be filtered.
Although some current circuits filter active high glitches and some current circuits allow the size of the glitches to be a variable, the capabilities of these circuits are limited. There is a need for circuits to filter both active high and active low glitches; especially, to handle the short glitches that may occur at the positive edge of the clock. There is also a need for a circuit that reduces the amount of on-chip real estate by minimizing the number of gates and/or switches.
Therefore, it would be desirable to provide a method of signal filtering and a filter circuit that efficiently and reliably removes both active high and active low glitches and allows adjustability of the idle period.